FIG. 1 is a longitudinal cross-section of a conventional bottom lead semiconductor package. As shown in this drawing, a conventional bottom lead semiconductor package includes a semiconductor chip 1, and a lead 2 composed of a plurality of substrate-connected leads 2a on top surface of which the semiconductor chip 1 is mounted and the bottom surface of which is connected to the substrate (not illustrated). A plurality of chip-connected leads 2b extends from the substrate-connected leads 2a to be wire-bonded to the semiconductor chip 1.
An adhesive 3 bonds the semiconductor chip 1 on the top surface of the substrate-connected lead 2a of the lead 2. A plurality of wires 5 electrically connects the chip pads/bonding pads (not illustrated) of the semiconductor chip 1 with the chip-connected leads 2b of the lead 2. A molding resin 4 molds a predetermined area including the wire-bonded semiconductor chip 1 and the two kinds of leads 2a, 2b of the lead 2 such that the bottom surfaces of the substrate-connected leads 2a of the lead frame are exposed on the bottom surface of the package body. The substrate-connected leads 2a of the lead 2 are down-set from the chip-connected leads 2b at a predetermined depth.
The semiconductor package having the above construction is described in detail in U.S. Pat. No. 5,428,248, assigned to the assignee of the present invention and whose disclosure is incorporated herein by reference. However, in the above conventional semiconductor package, when the chip pads are located at the sides of the semiconductor chip, a wire bonding can be carried out, but when the chip pads are located at the center thereof, it is not possible to carry out a wire bonding.